Electronic systems are used in numerous devices including Personal Computers (PC), servers, routers, hubs, switches, line cards, cellular telephones, Personal Data Assistants (PDA), electronic gaming devices, High Definition Televisions (HDTV), as well as industrial devices, automotive devices, and others. The primary technology drivers for these electronic systems are digital logic and control, semiconductor memory, Input/Output (I/O) and mixed signal (analog and digital) technologies. Examples of stand alone products include micro processors/controllers, Dynamic Random Access Memory (DRAM), SRAM, flash EEPROM, A/D converters etc. Examples of embedded products include multiple integrated circuits (IC) as SIC (System-In-Chip) or monolithic IC as SOC (System-On-Chip).
For well over three decades, semiconductor memories—such as, for example, DRAM'S, SRAM'S, ROM'S, EPROM'S, EEPROM'S, Flash EEPROM'S, Ferroelectric RAM'S, MAGRAM'S and others—have played a vital role in many electronic systems. Their functions for data storage, code (instruction) storage, and data retrieval/access (Read/Write) continue to span a wide variety of applications. Usage of these memories in both stand alone/discrete memory product forms, as well as embedded forms such as, for example, memory integrated with other functions like logic, in a module or monolithic IC, continues to grow. Cost, operating power, bandwidth, latency, ease of use, the ability to support broad applications (balanced vs. imbalanced accesses), and nonvolatility are all desirable attributes in a wide range of applications.
From a few kilobits (kb) of storage on a monolithic IC in the 1970's, semiconductor technology has come very far in density per memory chip. 1 Gigabit (GB) per monolithic IC is practical today in volatile Read/Write RAM'S like DRAM'S, as well as nonvolatile Read/Write memories like flash EEPROM. However, the granularity of access has not kept pace. Even though multibank IC's are available today, no more than 32 bits can be accessed at a time. Effectively, only one bank is available at a time for R/W; the other banks are non-accessible for substantially simultaneous operations. Access and cycle times have improved providing higher bandwidth with restrictions like ‘column pre-fetch’, ‘open page’ and ‘specialized I/O interface’ (DDR, QDR, RambusTM) etc. However, random latency—the ability to access any random location anywhere in the memory—is still an issue. With low voltage and battery operation becoming mandatory for portability, significant strides have yet to be made towards reducing power and latency. For example, mobile SDRAMs, such as for example those offered by Micron and others, have made some steps in reducing “stand by power”. However, reducing operating power still remains an issue in such memories.
In a commercially available DRAM, organized row by column such as in a matrix, when a row is opened (equal to one “page”) between one to four kilobits are available for fast random access once the “page” is opened. However, communications memories are not efficient with open page architecture for various reasons. First, unlike unbalanced Read/Write in computing system memory where Reads may dominate Writes by better than three to one, communication memories require balanced Read/Write where the number of Reads roughly equal the number of Writes. Second, the egress (outgoing) of packet memory content is completely random and unpredictable in communications memory. Thus, for these reasons random latency for any packet, or part of a packet, dictates useful bandwidth rather than the ability to quickly access a restricted addressing space such as in an open page. Additionally, before a new page can be opened (as in a DRAM), the existing or current page has to be closed, and the entire bank precharged. Hence, if an individual bank has 64 Mb density, even if one needs to only access 16 new bits in a row, one has to precharge the whole bank, which uses power and increases the temperature of the memory device.
Although, bandwidth, latency, cost, power, and form factor are all important, low power is key for mobile applications. Reducing operating power, as density and speeds increase for new generation devices, is a major concern. Asynchronous operation in DRAM'S, SRAM'S and flash EEPROM'S is the currently preferred option to reduce operating power—however, it penalizes access time and performance. Synchronous operation, on the other hand, requires ‘activation and precharge of millions of nodes in an integrated circuit (IC) thereby incurring high power costs. In CMOS designs, for example, operating power is approximately equal to CV2f, where f is the frequency, C is the capacitance (of all kinds) and V is the voltage. Reducing V and C has limits. For better performance generally f has to increase, making it more difficult to reduce operating power at the same time.
Multibank memories are common in DRAM, SRAM and flash. Predetermined (e.g. prefetched) bursts of data and “open page”, have been common in both DRAM and SRAM (such as for example Rambus™, DDR, QDR and others) to improve bandwidth. RLDRAM™ and FCRAM™ are two examples of bandwidth and latency-thrust. Round-robin schemes may also be used to reduce power but do not allow for random row access since access is restricted to each memory bank in a predetermined order. Thus, random row access time is lengthened on average.
In U.S. Pat. No. 5,828,610 dated Oct. 27, 1998 issued to Rogers et al, a Static RAM (SRAM) is disclosed. The SRAM is described as being capable of selectively precharging a data word prior to a read access operation on that data word, in order to conserve power. However, there is no teaching or suggestion for selectively precharging prior to a write access operation. It also does not teach or suggest a method of selectively precharging a single column of memory cells. Further, despite showing selective precharging, the operation of Roger's SRAM, as well as other standard memory not utilizing selective precharge, requires that one access cycle complete before another memory segment can be accessed. This manner of operation results in added latency. Additionally, SRAM in general is not as dense as other forms of memory, such as DRAM. Therefore, SRAM is less affected by soft errors than are more dense forms of memory such as modern DRAM. Beside sensitivity to soft errors, traditional SRAM unlike DRAM, typically does not have to support various kinds of burst mode operations